The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Sep. 22, 2022
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Wonse Lee, Yongin-si, KR;

Kyunghoon Kim, Yongin-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/00 (2023.01); H01L 23/58 (2006.01); H10D 1/68 (2025.01); H10K 59/121 (2023.01); H10K 59/126 (2023.01); H10K 59/131 (2023.01); G09G 3/3258 (2016.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01);
U.S. Cl.
CPC ...
H10K 59/126 (2023.02); H01L 23/585 (2013.01); H10D 1/692 (2025.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/131 (2023.02); H10K 59/1315 (2023.02); G09G 3/3258 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 2310/0202 (2013.01); H10D 86/441 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01);
Abstract

A display apparatus including a shielding conductive layer is disclosed. The display apparatus includes a substrate, a driving thin film transistor disposed on the substrate, wherein the driving thin film transistor includes a driving semiconductor layer and a driving gate electrode, a scan line overlapping the substrate and extending in a first direction, a data line extending in a second direction crossing the first direction, wherein the data line is insulated from the scan line by an insulating layer, a node connection line disposed on a same layer as the scan line, and a shielding conductive layer disposed between the data line and the node connection line, in which a first end of the node connection line is connected to the driving gate electrode via a first node contact hole.


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