The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Dec. 14, 2020
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Tatsuya Onuki, Kanagawa, JP;

Munehiro Kozuma, Kanagawa, JP;

Takeshi Aoki, Kanagawa, JP;

Takanori Matsuzaki, Kanagawa, JP;

Yuki Okamoto, Kanagawa, JP;

Masashi Oota, Kanagawa, JP;

Shuhei Nagatsuka, Kanagawa, JP;

Hitoshi Kunitake, Kanagawa, JP;

Shunpei Yamazaki, Tokyo, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); G06N 3/02 (2006.01);
U.S. Cl.
CPC ...
H10D 30/6756 (2025.01); G06N 3/02 (2013.01); H10D 30/673 (2025.01);
Abstract

To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.


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