The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Mar. 21, 2019
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Guilin Liu, San Jose, CA (US);

Fitsum A. Reda, Santa Clara, CA (US);

Kevin Shih, Santa Clara, CA (US);

Ting-Chun Wang, San Jose, CA (US);

Andrew Tao, Los Altos, CA (US);

Bryan Catanzaro, Sunnyvale, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/00 (2022.01); G06N 3/045 (2023.01); G06N 3/08 (2023.01); G06N 20/10 (2019.01); G06N 20/20 (2019.01); G06T 3/4007 (2024.01); G06T 5/20 (2006.01); G06T 5/77 (2024.01); H04N 19/132 (2014.01); H04N 19/139 (2014.01); H04N 19/172 (2014.01); H04N 19/587 (2014.01);
U.S. Cl.
CPC ...
H04N 19/139 (2014.11); G06N 3/045 (2023.01); G06N 3/08 (2013.01); G06N 20/10 (2019.01); G06N 20/20 (2019.01); G06T 3/4007 (2013.01); G06T 5/20 (2013.01); G06T 5/77 (2024.01); H04N 19/132 (2014.11); H04N 19/172 (2014.11); H04N 19/587 (2014.11); G06T 2207/20081 (2013.01); G06T 2207/20084 (2013.01);
Abstract

A neural network architecture is disclosed for performing image in-painting using partial convolution operations. The neural network processes an image and a corresponding mask that identifies holes in the image utilizing partial convolution operations, where the mask is used by the partial convolution operation to zero out coefficients of the convolution kernel corresponding to invalid pixel data for the holes. The mask is updated after each partial convolution operation is performed in an encoder section of the neural network. In one embodiment, the neural network is implemented using an encoder-decoder framework with skip links to forward representations of the features at different sections of the encoder to corresponding sections of the decoder.


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