The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Jul. 05, 2023
Applicant:

Skyworks Solutions, Inc., Irvine, CA (US);

Inventor:

Alexander Cherkassky, Hollis, NH (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/20 (2006.01); H03L 7/099 (2006.01); H03M 1/06 (2006.01); H03L 7/081 (2006.01); H03L 7/197 (2006.01);
U.S. Cl.
CPC ...
H03M 1/207 (2013.01); H03L 7/0992 (2013.01); H03M 1/0648 (2013.01); H03L 7/0814 (2013.01); H03L 7/1974 (2013.01);
Abstract

An interpolative divider divides an input clock signal according to a divide ratio and supplies an output clock signal. An integer divider receives the input clock signal and supplies an integer divider output signal. A phase interpolator is coupled to the integer divider and delays the integer divider output signal according to a quantization error. The phase interpolator includes first and second current sources. The first current source turns on k unit current elements during a first part of a charging cycle to charge a first capacitor to a first voltage, 0≤k≤M, k and M are integers, and k is determined by the digital quantization error. The second current source turns on k+M unit elements to charge a second capacitor during a second part of the charging cycle. The output clock signal transitions when the first voltage equals the second voltage.


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