The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Dec. 01, 2022
Applicant:

Psemi Corporation, San Diego, CA (US);

Inventors:

Aichen Low, Cambridge, MA (US);

Walid Fouad Mohamed Aboueldahab, Wokingham, GB;

Gregory Szczeszynski, Hollis, NH (US);

Assignee:

pSemi Corporation, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/00 (2006.01); G05F 1/565 (2006.01); G05F 3/26 (2006.01); H02M 3/07 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 3/073 (2013.01); G05F 1/565 (2013.01); G05F 3/262 (2013.01); H02M 1/0025 (2021.05); H02M 3/072 (2021.05);
Abstract

Circuit embodiments for a switched-capacitor power converter, and/or methods of operation of such a converter, that robustly deal with various startup scenarios, are efficient and low cost, and have quick startup times to steady-state converter operation. Embodiments prevent full charge pump capacitor discharge during shutdown of a converter and/or rebalance charge pump capacitors during a startup period before switching operation by discharging and/or precharging the charge pump capacitors. Embodiments may include a dedicated rebalancer circuit that includes a voltage sensing circuit coupled to an output voltage of a converter, and a balance circuit configured to charge or discharge each charge pump capacitor towards a target steady-state multiple of the output voltage of the converter as a function of an output signal from the voltage sensing circuit indicative of the output voltage. Embodiments prevent or limit current in-rush to a converter during a startup state.


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