The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Jun. 13, 2023
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Angelo Scuderi, Catania, IT;

Nicola Marinelli, Mediglia, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/66 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 24/17 (2013.01); H01L 23/5386 (2013.01); H01L 23/66 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 25/0655 (2013.01); H01L 25/105 (2013.01); H01L 2223/6627 (2013.01); H01L 2223/6677 (2013.01); H01L 2223/6683 (2013.01); H01L 2224/14133 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/17133 (2013.01); H01L 2224/48105 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73257 (2013.01); H01L 2924/1423 (2013.01);
Abstract

An electronic device has a plurality of integrated circuits fixed to a support between transmitting and receiving antennas. An integrated circuit generates a synchronization signal supplied to the other integrated circuits. Each integrated circuit is formed in a die integrating electronic components and overlaid by a connection region according to the Flip-Chip Ball-Grid-array or embedded Wafer Level BGA. A plurality of solder balls for each integrated circuit is electrically coupled to the electronic components and bonded between the respective integrated circuit and the support. The solder balls are arranged in an array, aligned along a plurality of lines parallel to a direction, wherein the plurality of lines comprises an empty line along which no solder balls are present. A conductive synchronization path is formed on the support and extends along the empty line of at least one integrated circuit, between the solder balls of the latter.


Find Patent Forward Citations

Loading…