Memory device and memory system for using read compensation scheme and operating method of the same

Abstract

A memory device includes: a plurality of memory blocks each including a plurality of word lines, a control operation circuit configured to perform a read operation on each of the plurality of word lines, and a control logic configured to: store a plurality of default levels, which respectively correspond to the memory blocks, in an information storage region therein, control the control operation circuit to perform one of a first read operation using a selected default level corresponding to a selected block and a second read operation using an adjusted level smaller than the selected default level, reset the adjusted level to the selected default level when a number of times that the second read operation is passed is greater than a number of times that the first read operation is passed, by a reference number of times or more, and store the reset level in the information storage region.