Pipeline architecture for bitwise multiplier-accumulator (mac)

Abstract

A unit for accumulating a plurality of multiplied bit values includes a first row and a second row of input units, a bit-wise multiplier and a bit-wise accumulator. The first row receives a pipeline of the bits of a multiplicand A and the second row, to the left of the first row, receives a pipeline of the bits of a multiplicand B. The bit-wise multiplier, below the first row of input units, includes multiplier bit-line processors formed into rows and columns. Some rows of the bit-wise multiplier bit-wise multiplies bits of a current multiplicand A with one bit of a current multiplicand B and some rows of the bit-wise multiplier handle sum and carry values between the bits. The bit-wise accumulator, to the right of the bit-wise multiplier, includes a column of accumulator bit-line processors. Each accumulator bit-line processor accumulates output of a row of the bit-wise multiplier.