Hardware guided software prefetch insertion

Abstract

Generally disclosed herein is an approach for identifying target code locations for software prefetching instructions based on hardware prefetching information. The target code locations can be identified based on the locations where the hardware prefetchers were designed to prefetch loads. Hardware cache events related to processor events for different caches can be monitored for cache misses in a system running when hardware prefetchers are active and inactive. Code locations that may benefit from the use of the hardware prefetchers may be determined based on an ablation study. The identified code locations may be treated as recognized memory access patterns. Software prefetchers can be configured to use these memory access patterns for prefetching data while avoiding an extended time required to identify memory access patterns (i.e. a warm-up period) and fetching in locations where hardware prefetching is beneficial.