The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Sep. 26, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Sangsu Park, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G01R 31/26 (2020.01); G11C 16/04 (2006.01); G11C 16/16 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
G01R 31/2637 (2013.01); G11C 16/0483 (2013.01); G11C 16/16 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H10B 80/00 (2023.02); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A bonding quality test circuit includes a switching circuit configured to provide a connection between a sensing node and a bonding node, the bonding node corresponding to a first end of a bonding resistor that is between a line provided to a memory device and a peripheral circuit, a precharging circuit configured to provide a precharge voltage to the line and the sensing node when the precharging circuit is connected to the line and the sensing node by the switching circuit, a latch circuit that includes a first node configured to provide a control output signal to the precharging circuit and a second node configured to have a voltage that is phase inverted with respect to a voltage of the control output signal, and a first transistor configured to provide an output signal according to the sensing node when the first transistor is connected to the second node.


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