The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

May. 05, 2023
Applicant:

Maxeon Solar Pte. Ltd., Singapore, SG;

Inventor:

David D. Smith, Campbell, CA (US);

Assignee:

Maxeon Solar Pte. Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 10/14 (2025.01); H10F 71/00 (2025.01); H10F 77/122 (2025.01); H10F 77/70 (2025.01);
U.S. Cl.
CPC ...
H10F 10/14 (2025.01); H10F 71/1221 (2025.01); H10F 77/122 (2025.01); H10F 77/707 (2025.01);
Abstract

A solar cell, and methods of fabricating said solar cell, are disclosed. The solar cell can include a substrate having a light-receiving surface and a back surface. The solar cell can include a first semiconductor region of a first conductivity type disposed on a first dielectric layer, wherein the first dielectric layer is disposed on the substrate. The solar cell can also include a second semiconductor region of a second, different, conductivity type disposed on a second dielectric layer, where a portion of the second thin dielectric layer is disposed between the first and second semiconductor regions. The solar cell can include a third dielectric layer disposed on the second semiconductor region. The solar cell can include a first conductive contact disposed over the first semiconductor region but not the third dielectric layer. The solar cell can include a second conductive contact disposed over the second semiconductor region, where the second conductive contact is disposed over the third dielectric layer and second semiconductor region. In an embodiment, the third dielectric layer can be a dopant layer.


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