The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2025
Filed:
Apr. 25, 2025
Shandong Jianzhu University, Jinan, CN;
Xiaoyan Li, Jinan, CN;
Changwei Qin, Jinan, CN;
Chengdong Li, Jinan, CN;
Han Xu, Jinan, CN;
Zhiyuan Chu, Jinan, CN;
Chuanjing Hou, Jinan, CN;
Hongchao Bai, Jinan, CN;
Dongjiang Yang, Jinan, CN;
Lei Yang, Jinan, CN;
SHANDONG JIANZHU UNIVERSITY, Jinan, CN;
Abstract
The present invention provides a method for cooperatively suppressing a common-mode voltage and current harmonics of coupled three-level inverters, comprising: based on amplitude and phase angle of reference voltage vector, determining sector and region in which the reference voltage vector is located; selecting four basic voltage vectors with low common-mode voltage amplitudes to synthesize the reference voltage vector; writing volt-second balance equation based on selected basic voltage vectors, and calculating duty cycles thereof; and based on sector and region in which reference voltage vector is located, set value of voltage difference across capacitors on direct current side, and actual value of voltage difference across capacitors on direct current side, (1) updating duty cycles of basic voltage vectors, to realize separate control of capacitor voltage; and (2) designing and converting switching sequence into PWM drive signal of power switch, to control the coupled three-level inverter to operate.