The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Sep. 22, 2023
Applicant:

Juniper Networks, Inc., Sunnyvale, CA (US);

Inventors:

Jaspal S. Gill, Tracy, CA (US);

Katsuhiro Okamura, Watsonville, CA (US);

Varaha Venkata Satya Narayana Jagarapu, Sunnyvale, CA (US);

David K. Owen, Livermore, CA (US);

Assignee:

Juniper Networks, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02J 3/46 (2006.01);
U.S. Cl.
CPC ...
H02J 3/46 (2013.01);
Abstract

In some implementations, a power balancing device may monitor a power supply module (PSM) that includes multiple power supply channels. The PSM may be part of a power supply system for a network component that includes multiple PSMs, with each of the multiple PSMs being associated with a maximum output power. The power balancing device may determine that at least one power supply channel, of the multiple power supply channels, is inoperable. The power balancing device may determine, based on determining that the at least one power supply channel is inoperable, a revised maximum output power for the PSM based on a maximum allowable input current to each power supply channel, of the multiple power supply channels. The power balancing device may cause the PSM to output a power that is less than or equal to the revised maximum output power.


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