The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Dec. 14, 2022
Applicant:

Tron Future Tech Inc., Hsinchu, TW;

Inventors:

Kuan-Neng Chen, Hsinchu, TW;

Han-Wen Hu, Hsinchu County, TW;

Yi-Chieh Tsai, Taoyuan, TW;

Yu-Jiu Wang, Hsinchu, TW;

Li Han Chang, Hsinchu, TW;

Assignee:

TRON FUTURE TECH INC., Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01Q 1/38 (2006.01); H01L 23/00 (2006.01); H01L 25/03 (2006.01); H01Q 3/36 (2006.01);
U.S. Cl.
CPC ...
H01Q 1/38 (2013.01); H01L 25/03 (2013.01); H01Q 3/36 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01);
Abstract

An antenna package structure is provided. The antenna package structure includes a glass substrate, an interconnect structure, a plurality of semiconductor chips, and an antenna array structure. The glass substrate has a first surface and a second surface opposite to the first surface. The interconnect structure is disposed over the first surface of the glass substrate. The plurality of semiconductor chips are mounted over the interconnect structure. The antenna array structure is formed on the second surface of the glass substrate. Furthermore, the plurality of semiconductor chips are coupled to the antenna array structure through the interconnect structure and the glass substrate.


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