The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Aug. 08, 2022
Applicants:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Research & Business Foundation Sungkyunkwan University, Suwon-si, KR;

Inventors:

Jung Hoon Chun, Suwon-si, KR;

Ji Ho Song, Seoul, KR;

Yoonmyung Lee, Suwon-si, KR;

Ju A Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/50 (2006.01); G06N 3/06 (2006.01); G11C 11/54 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/54 (2013.01); G06N 3/061 (2013.01); G11C 13/004 (2013.01);
Abstract

A neural network method and device are included, A neural network circuit includes a synaptic memory cell including a resistive memory element, which is disposed along an output line and which can have a first resistance value and a second resistance value as a resistance value, the synaptic memory cell generates a column signal, based on the resistance value of the resistive memory element and an input signal received via an input line, a reference memory cell including a reference memory element, which is disposed along a reference line and which has a resistance value that is a ratio of the first and second resistance values, the reference memory cell generates a reference signal, based on the resistance value of the reference memory element and the input signal, and an output circuit generates an output signal for the output line based on the column signal and the reference signal.


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