The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Oct. 14, 2022
Applicant:

Quantum Circuits, Inc., New Haven, CT (US);

Inventors:

Samuel H. Moseley, Jr., New Haven, CT (US);

Pratheev Sabaratnam Sreetharan, Concord, MA (US);

Robert John Schoelkopf, Iii, Madison, CT (US);

Assignee:

Quantum Circuits, Inc., New Haven, CT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 10/40 (2022.01); H01P 1/22 (2006.01); H01P 1/30 (2006.01); H01P 3/08 (2006.01); H04B 10/70 (2013.01);
U.S. Cl.
CPC ...
G06N 10/40 (2022.01); H01P 1/30 (2013.01); H01P 3/081 (2013.01); H04B 10/70 (2013.01); H01P 1/227 (2013.01);
Abstract

An interface between cryogenic computational hardware and room temperature computational hardware includes a plurality of discrete stages, including a first stage at room temperature and a last stage at a cryogenic temperature. Each successive stage is configured for operation at a corresponding refrigeration temperature that is lower than the refrigeration temperature of each preceding stage and includes a set of planar transmission lines. The transmission lines of any given stage other than the first stage are proximally coupled to and contiguous with the transmission lines of an immediately preceding stage. The transmission lines of the first stage are proximally coupled to the room temperature computational hardware, and the transmission lines of the last stage are proximally coupled to the cryogenic computational hardware. Each stage has shielding configured to block electromagnetic radiation external to such stage.


Find Patent Forward Citations

Moseley, Jr., Samuel. (2025). Interface between cryogenic computational hardware and room temperature computational hardware (U.S. Patent No. 12417398). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12417398

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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