The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

May. 15, 2024
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Anup Holey, San Jose, CA (US);

Wishwesh Anil Gandhi, Sunnyvale, CA (US);

Sujoyita Kaushikkar, San Jose, CA (US);

Karan Mehra, Apex, NC (US);

Daniel Glenn Robinson, Cary, NC (US);

Sami Olavi Johannes Kiminki, Espoo, FI;

Alexander Michael Waterman, Westlake Hills, TX (US);

Mark Hairgrove, San Jose, CA (US);

Jeff Smith, Barrington, RI (US);

Liang Yin, Palo Alto, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0815 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0815 (2013.01);
Abstract

A processing device including a first cache is coupled to a system memory and a parallel processing unit (PPU) including a second cache. An operation to modify cache lines of the second cache associated with a first aperture of the system memory is received. A first subset of cache lines of the second cache is identified. The first subset of cache lines is associated with the first aperture of the system memory and is different from a second subset of cache lines of a second aperture of the system memory. The first subset of cache lines is modified as specified by the cache operation.


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