The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Mar. 13, 2024
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Ming Liang Milton Lei, Santa Clara, CA (US);

Jeffery Michael Schottmiller, Raleigh, NC (US);

Manan Patel, San Jose, CA (US);

Pritha Ghoshal, Apex, NC (US);

Michael Alan Fetterman, Lancaster, MA (US);

Robert Ohannessian, Jr., Austin, TX (US);

Praveen Kumar Kaushik, Karnataka, IN;

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0804 (2016.01); G06F 12/0868 (2016.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0804 (2013.01); G06F 12/0868 (2013.01); G06F 12/0875 (2013.01);
Abstract

A first instruction to load a first data into a first register file associated with a first subpartition unit is received. A second instruction to load the first data into a second register file associated with a second subpartition unit is received. The first instruction and the second instruction are coalesced into a first entry of a request coalescer based on instruction identifiers. The first entry is associated with the first data. Responsive to a determination that the first data is available in the cache, the first data is multicast from the cache to the first register file and the second register file.


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