The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2025
Filed:
Jul. 18, 2023
Sandisk Technologies, Inc., Milpitas, CA (US);
Shuli Shmaya, Ks, IL;
Eran Moshe, Kfar Saba, IL (US);
Sandisk Technologies, Inc., Milpitas, CA (US);
Abstract
Instead of allowing an electrostatic discharge (ESD) event to cause a lost clock signal sync due effects of the ESD event causing an SSD to enter low power mode, utilizing ESD detection can be used to stop the reference clock signal to avoid involuntary low power mode. When an ESD event occurs, an ESD antenna sensor will selectivity disable sensitive signals and the reference clock signal. Once the ESD detector recognizes an ESD event has occurred, the device is able to enter freeze mode. While the reference clock signal is in freeze mode, the input signals are bypassed to avoid lost clock signal sync. Once the ESD event is done, the controller notifies the host to restart the reference clock signal and resume clock signal sync.