The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2025
Filed:
Mar. 29, 2022
Amazon Technologies, Inc., Seattle, WA (US);
Sheng Xu, Mountain View, CA (US);
Hongbin Zheng, San Jose, CA (US);
Qingrui Liu, San Jose, CA (US);
Jason Xiong, Albuquerque, NM (US);
Amazon Technologies, Inc., Seattle, WA (US);
Abstract
Techniques for determining a compatible data layout for a computational flow being executed on an integrated circuit device may include obtaining a representation of a set of connected nodes representing loopnests in a compute flow graph. Those of the nodes in the set of connected nodes that are associated with operators having a fixed data layout can be initialized into a set of layout groups. A set of merging operations can then be iteratively performed to form a single layout group from the set of connected nodes. The set of merging operations may include identifying a set of frontier nodes adjacent to the set of layout groups, determining an initialization cost of each of the frontier nodes, selecting a frontier node having a lowest initialization cost, and merging the selected frontier node with one or more adjacent layout groups to form a new layout group having a compatible data layout.