The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Sep. 24, 2020
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventor:

Benjamin Tsien, Santa Clara, CA (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/3228 (2019.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3228 (2013.01); G06F 9/4893 (2013.01);
Abstract

Systems, apparatuses, and methods for efficient power management of a multi-node computing system are disclosed. A computing system includes multiple nodes that receive tasks to process. The nodes include a processor, local memory, a power controller, and multiple link interfaces for transferring messages with other nodes across links. Using a distributed approach for power management, negotiation for powering down components of the computing system occurs without performing a centralized system-wide power down. Each node is able to power down its links, its processor and other components regardless of whether other components of the computing system are still active or powered up. A link interface initiates power down of a link with delay or without delay based on a prediction of whether a link idle condition leads to the link interface remaining idle for at least a target idle threshold period of time.


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