The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Jul. 30, 2023
Applicant:

Dell Products L.p., Round Rock, TX (US);

Inventors:

Doug Messick, Austin, TX (US);

Craig Klein, Elgin, TX (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/28 (2006.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 1/263 (2013.01); G06F 1/26 (2013.01); G06F 1/28 (2013.01); G06F 11/3058 (2013.01);
Abstract

An information handling system has a regulator, a power indication network, a PSU, and a BMC. The regulator receives a system power level indication and provides power to a processor based upon the power indication. The power indication network includes a first resistor stage to shunt the power indication to a ground plane, and a second resistor stage selectably to shunt the power indication to the ground plane. The PSU provides the power indication as a current output where a level of current output indicates a power level provided by the PSU. The BMC determines a power budget for the information handling system, calculates a number of resistor stages to couple to the ground plane based on the power budget, when the number is less than or equal to one, selects the second resistor stage to be uncoupled from the ground plane, and when the number is greater than one, to select the second resistor stage to be coupled to the ground plane.


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