The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Apr. 07, 2023
Applicant:

Hannstar Display Corporation, Taipei, TW;

Inventors:

Mu-Kai Kang, Tainan, TW;

Cheng-Yen Yeh, Taichung, TW;

Sz-Kai Huang, Taichung, TW;

Jing-Xuan Chen, Tainan, TW;

Yen-Chung Chen, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01);
U.S. Cl.
CPC ...
G02F 1/136286 (2013.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01);
Abstract

A display panel includes a substrate, pixels, gate lines, a gate connecting line, a common line and a compensation electrode. The pixels are disposed on the substrate. The gate lines are disposed on the substrate and are configured to receive scan signals. The number of pixels coupled to a first gate line of the gate lines is less that the number of pixels coupled to a second gate line of the gate lines. The gate connecting line is electrically connected to the first gate line. The common line is disposed under the gate connecting line, and is configured to receive a common voltage signal. The compensation electrode is disposed over the gate connecting line, and is configured to receive the common voltage signal. The common line, the gate connecting line and the compensation electrode are overlapped.


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