The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2025

Filed:

Jul. 27, 2023
Applicant:

Parabellum Strategic Opportunities Fund Llc, Wilmington, DE (US);

Inventor:

Jhon Jhy Liaw, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/0243 (2025.01); H10D 30/6212 (2025.01); H10D 30/6757 (2025.01); H10D 62/116 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/021 (2025.01); H10D 64/679 (2025.01); H01L 21/30604 (2013.01); H01L 21/3065 (2013.01);
Abstract

The present disclosure provides an integrated circuit (IC) device, including: a semiconductor substrate having a top surface; a first source/drain feature and a second source/drain feature disposed on the semiconductor substrate; and a plurality of semiconductor layers including a first semiconductor layer and a second semiconductor layer. Each of the first semiconductor layer and the second semiconductor layer extends longitudinally in a first direction and connects the first source/drain feature and the second source/drain feature. The first semiconductor layer is stacked over the second semiconductor layer in a second direction perpendicular to the first direction. A length of the first semiconductor layer along the first direction is less than a length of the second semiconductor layer along the first direction. The IC device further includes a gate structure engaging center portions of the first semiconductor layer and the second semiconductor layer.


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