The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2025

Filed:

Oct. 30, 2020
Applicant:

Teledyne Digital Imaging, Inc., Waterloo, CA;

Inventors:

Hyun Jung Lee, Waterloo, CA;

Paul Donegan, Kitchener, CA;

Nixon O, Winnipeg, CA;

Sung Kuk Hong, Kitchener, CA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 25/78 (2023.01); H04N 25/616 (2023.01); H04N 25/68 (2023.01); H04N 25/711 (2023.01); H04N 25/75 (2023.01); H04N 25/768 (2023.01); H04N 25/77 (2023.01);
U.S. Cl.
CPC ...
H04N 25/78 (2023.01); H04N 25/768 (2023.01); H04N 25/77 (2023.01);
Abstract

Provided are apparatus, methods and techniques to perform a readout of a plurality (N) of Time Delay and Integration (TDI) pixel registers to receive respective signal charges at a plurality (N) of sense nodes (SNs). The readout uses a plurality (N) of charge steering (CST) gates to steer and demultiplex respective charges from respective pixel registers to corresponding SNs. Output is provided from the SNs for producing respective digital values (e.g. through parallel conversion using ADCs). In an embodiment, charges are transferred vertically to the CSTs for demultiplexing horizontally to the SNs. The CSTs may be configured in a multi-stage configuration to assist with good charge transfer. The CSTs may be associated with a barrier implant to assist with proper charge steering.


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