The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2025
Filed:
May. 13, 2022
Applicant:
Samsung Electro-mechanics Co., Ltd., Suwon-si, KR;
Inventors:
Yun Tae Lee, Suwon-si, KR;
Jin Won Lee, Suwon-si, KR;
Assignee:
SAMSUNG ELECTRO-MECHANICS CO., LTD., Suwon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49833 (2013.01); H01L 23/145 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H01L 24/16 (2013.01); H01L 2224/16013 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01);
Abstract
A semiconductor package includes: a semiconductor chip including a front end of line (FEOL) layer and a first back end of line (BEOL) layer disposed on the FEOL layer; and a printed circuit board including a wiring layer and a second BEOL layer disposed on the wiring layer, wherein the semiconductor chip is mounted on the printed circuit board so that the first and second BEOL layers are connected to each other while facing each other, and the second BEOL layer includes a wiring for power transmission.