Ultra-low-voltage static random access memory (sram) cell for eliminating half-select disturbance under bit interleaving structure

Abstract

An ultra-low-voltage static random access memory (SRAM) cell for eliminating half-select-disturbance under a bit interleaving structure includes a cross-coupled inverter pair, two N-type write transistors NMand NM, two P-type write transistors PMand PM, and two N-type transistors NMand NM, where the two N-type transistors NMand NMform a readout path. The present disclosure can be applied to applications with a storage requirement at an ultra-low voltage, especially applications with certain requirements for an access speed and reliability of an SRAM at a low voltage. Compared with other different SRAM cells, the ultra-low-voltage SRAM cell can achieve higher read and write working frequencies with similar energy consumptions.