Context-aware bit-stream generator for deterministic stochastic computing

Abstract

Disclosed herein are three context-aware architectures to accelerate the three state-of-the-art deterministic methods of SC. The proposed designs employ a control unit to extract the minimum bit-width required to precisely represent each input data. The lengths of bit-streams are reduced to the minimum lengths required to precisely represent each input data. The noise-tolerance property of the designs is preserved as each bit-flip can only introduce a least significant bit error. The proposed designs achieve a considerable improvement in the processing time at a reasonable hardware cost overhead. The proposed designs make the deterministic bit-stream processing more appealing for applications that expect highly accurate computation and also for error-tolerant applications.