The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Sep. 02, 2021
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yang Zhou, Beijing, CN;

Linhong Han, Beijing, CN;

Huijuan Yang, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 86/40 (2025.01); G09G 3/3233 (2016.01); H10K 59/131 (2023.01); H10K 71/00 (2023.01); H10K 59/12 (2023.01);
U.S. Cl.
CPC ...
H10D 86/411 (2025.01); G09G 3/3233 (2013.01); H10K 71/00 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); H10K 59/1201 (2023.02); H10K 59/131 (2023.02);
Abstract

Provided is a display substrate, including a capacitance compensation region which is provided with a first capacitance compensation unit. The first capacitance compensation unit includes a semiconductor structure, a first metal structure, and a second metal structure sequentially arranged on a base substrate. An insulation layer between the semiconductor structure and the second metal structure is provided with a plurality of first via holes that are arranged along a first direction, and the second metal structure is connected to the semiconductor structure by means of the plurality of first via holes. The first metal structure includes a plurality of second gate lines extending along the first direction. In a second direction perpendicular to the first direction, a distance between two adjacent first via holes is at least greater than a sum of widths of two second gate lines.


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