The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Mar. 15, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jae Kyeong Jeong, Seoul, KR;

Min Tae Ryu, Hwaseong-si, KR;

Hyeon Joo Seul, Seoul, KR;

Sungwon Yoo, Hwaseong-si, KR;

Wonsok Lee, Suwon-si, KR;

Min Hee Cho, Suwon-si, KR;

Jae Seok Hur, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 23/00 (2006.01); H10B 12/00 (2023.01); H10D 30/47 (2025.01); H10D 30/67 (2025.01); H10D 62/80 (2025.01); H10D 99/00 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6755 (2025.01); H01L 24/08 (2013.01); H10B 12/05 (2023.02); H10B 12/50 (2023.02); H10D 30/475 (2025.01); H10D 30/477 (2025.01); H10D 30/478 (2025.01); H10D 30/6757 (2025.01); H10D 62/80 (2025.01); H10D 99/00 (2025.01); H01L 2224/08145 (2013.01);
Abstract

Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.


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