The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Dec. 02, 2022
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Ga Ram Choi, Icheon-si, KR;

Dae Hyun Kim, Icheon-si, KR;

Changhan Kim, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 41/27 (2023.01); H10B 51/20 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 41/27 (2023.02); H10B 51/20 (2023.02); H10B 63/34 (2023.02);
Abstract

There are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a doped semiconductor layer including an upper surface facing a first direction, a multifunctional stack including a plurality of interlayer insulating layers and a plurality of conductive layers stacked alternately with each other in the first direction above the doped semiconductor layer, the multifunctional stack including a groove, a liner insulating layer on a bottom surface of the groove, a liner semiconductor layer on the liner insulating layer, and a first electrode and a second electrode spaced apart from each other in the groove and extending in the first direction from the liner semiconductor layer.


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