The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Sep. 30, 2021
Applicant:

Chengdu Pbm Technology Ltd., Chengdu, CN;

Inventors:

Jack Zezhong Peng, Chengdu, CN;

Ke Wang, Chengdu, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/31 (2006.01); H01L 21/311 (2006.01); H10B 20/00 (2023.01); H10D 8/01 (2025.01);
U.S. Cl.
CPC ...
H10B 20/40 (2023.02); H01L 21/311 (2013.01); H10D 8/051 (2025.01);
Abstract

The present disclosure provides a method for manufacturing a fully self-aligned high-density 3D multi-layer memory, which relates to the technical field of memory manufacturing. The method includes the following steps: 1) forming a base structure; 2) grooving the base structure; 3) filling an insulating medium in the division groove; 4) deep-hole etching the insulating medium in step 3 to form memory cell holes discretely arranged along the division groove, where the insulating medium is present between adjacent memory cell holes, and conductive medium layers and insulating medium layers of the base structure are exposed in the memory cell holes; and 5) disposing various layers of medium required by a preset memory structure layer by layer onto the inner walls of the memory cell holes. The semiconductor memory manufactured according to the present disclosure has high storage density.


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