The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2025
Filed:
Aug. 11, 2023
Applicant:
Apple Inc., Cupertino, CA (US);
Inventors:
Saurabh P. Sinha, Austin, TX (US);
Shahzad Nazar, Fremont, CA (US);
Xin Miao, Saratoga, CA (US);
Emre Alptekin, San Jose, CA (US);
Assignee:
Apple Inc., Cupertino, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); H01L 23/528 (2006.01); H10D 30/63 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
H10B 10/125 (2023.02); H01L 23/5286 (2013.01); H10B 10/18 (2023.02); H10D 30/63 (2025.01); H10D 64/252 (2025.01); H10D 64/518 (2025.01); H10D 84/85 (2025.01); H10D 84/856 (2025.01); H10D 89/10 (2025.01); H10B 10/12 (2023.02);
Abstract
A memory device layout that implements SRAM cells with stacked transistors is disclosed. The memory utilizes both topside metal routing and backside metal routing for routing of bitlines between bit cells with stacked transistors and logic cells coupled to the bit cells.