Multi-stage digitally controlled delay line linearity enhancing by redundancy and randomization

Abstract

A circuit or reducing fractional spurs comprises a digital to time converter (DTC) comprising multiple delay stages electrically coupled to one another in series, configured such that each delay stage is binary switched till the code exceeds cell range and then it is fully turned ON, and thereafter it is moved to the next stage, each delay stage comprising a digitally controlled delay line (DCDL) having code-dependent integrated nonlinearity (INL), with the maximal value of the INL occuring at a mid-code position; and an offset stage comprising the DCDL electrically coupled to the DTC in series, configured to generate random codes for each required time delay of the DTC to ensure the probability of landing at the mid-code position is reduced and landing point is kept as far away as possible from the mid-code position for every required time delay, thereby improving the INL and the fractional spurs.