Memory device including row decoder

Abstract

A memory device includes a first semiconductor structure including pass transistors defined in a row decoder region of a substrate, a first bonding layer including first bonding pads, and bottom wiring layers disposed between the substrate and the first bonding layer; a second semiconductor structure including a second bonding layer including second bonding pads bonded to the first bonding pads, a memory cell array, and a top wiring layer disposed between the second bonding layer and the memory cell array; and global lines disposed in the row decoder region, and configured to transfer operating voltages to the pass transistors, wherein the bottom wiring layers include bottom wiring layers of a first tier and bottom wiring layers of a second tier disposed over the bottom wiring layers of the first tier, and the global lines are disposed in at least one of the bottom wiring layers of the first tier.