Source driver chip including or logic and and logic and display device

Abstract

A source driver chip and a display device are disclosed. The source driver chip includes an OR logic arithmetic unit, a clock buffer, a shift register, and an AND logic arithmetic unit. An OR logic operation is performed on a line latch signal and a first output data delay control enabling signal to obtain a second output data delay control enabling signal, and an AND logic operation is performed on an initial line latch sub-signals and the second output data delay control enabling signal, such that electrostatic interference of the line latch signal can be reduced.