The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

May. 04, 2023
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventor:

Atsushi Umezaki, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/18 (2006.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01); H03K 3/356 (2006.01); H03K 17/06 (2006.01); H03K 17/081 (2006.01); H03K 19/0185 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); G02F 1/1368 (2006.01); G02F 1/167 (2019.01); G09G 3/3225 (2016.01); G09G 3/34 (2006.01); H10D 30/67 (2025.01); H10K 59/12 (2023.01);
U.S. Cl.
CPC ...
G09G 3/20 (2013.01); G09G 3/36 (2013.01); G09G 3/3688 (2013.01); G11C 19/184 (2013.01); G11C 19/28 (2013.01); H03K 3/356 (2013.01); H03K 17/06 (2013.01); H03K 17/08104 (2013.01); H03K 19/018521 (2013.01); H10D 86/40 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); G02F 1/1368 (2013.01); G02F 1/167 (2013.01); G09G 3/3225 (2013.01); G09G 3/344 (2013.01); G09G 3/3648 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0876 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/043 (2013.01); G09G 2330/021 (2013.01); H10D 30/6755 (2025.01); H10K 59/12 (2023.02);
Abstract

Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.


Find Patent Forward Citations

Loading…