The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Apr. 01, 2021
Applicant:

Novasparks, Inc., New York, NY (US);

Inventors:

Pierre Gardrat, Paris, FR;

Elena Pugliese, Gentilly, FR;

Guillaume Taba, Saint Selve, FR;

Julien Girard, Saint Sebastien sur Loire, FR;

Camille Ribet, Rezé, FR;

Fei Li, Paris, FR;

Jonathan Clairembault, Vannes, FR;

Daniel Strul, Paris, FR;

Assignee:

NovaSparks, Inc., New York, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06Q 40/04 (2012.01); G06Q 30/0201 (2023.01);
U.S. Cl.
CPC ...
G06Q 40/04 (2013.01); G06Q 30/0201 (2013.01);
Abstract

The present disclosure provides techniques and associated systems for low-latency integrated circuit-based feed handler circuits and multi-market order book consolidator circuits. In some embodiments, integrated circuit-based feed handler circuits described herein can be configured to store aggregate quantities of instruments and/or determine round-lot price levels in a parallel hardware configuration. In some embodiments, integrated circuit-based order book consolidator circuits described herein can be configured to determine consolidated prices across multiple market data feeds and/or for different groups of markets in parallel hardware configurations. According to various embodiments, aspects of the present disclosure can be implemented using one or more FPGAs, ASICs, and/or combinations thereof.


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