The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Mar. 01, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Changho Choi, San Jose, CA (US);

Rajinikanth Pandurangan, Fremont, CA (US);

Ramzi Ammari, Santa Clara, CA (US);

Zongwang Li, Dublin, CA (US);

Yang Seok Ki, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 9/5016 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45579 (2013.01); G06F 2009/45583 (2013.01);
Abstract

A system is disclosed. The system may include a processor. The system may also include a first submission queue (SQ) and a second SQ. The first SQ may be associated with a first Quality of Service (QoS) level and the second SQ may be associated with a second QoS level, the first QoS level being different from the second QoS level. An application may be running on the processor and using a first namespace (NS). The processor may be configured to receive a first Non-Volatile Memory (NVM) Set create command to establish a first NVM Set associated with the first SQ. The processor may be further configured to receive a second NVM Set create command to establish a second NVM Set associated with the second SQ. The processor may be further configured to receive a first NS create command to establish a first NS associated with the first NVM Set. The processor may be further configured to receive a second NS create command to establish a second NS associated with the second NVM Set. The processor may be further configured to place an input/output (I/O) request sent from the application to at least one storage device in the first SQ based at least in part on the I/O request being associated with the first NS, the first NS being associated with the first NVM Set, and the first NVM Set being associated with the first SQ.


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