The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2025
Filed:
Apr. 20, 2023
Nvidia Corporation, Santa Clara, CA (US);
Miguel Rodriguez, Santa Clara, CA (US);
Suhas Satheesh, Santa Clara, CA (US);
Tezaswi Raja, Santa Clara, CA (US);
Nishit Harshad Shah, Santa Clara, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
Circuitry and a method of determining electrical characteristics of material local to a specific area of a semiconductor wafer. In one embodiment, the method includes sinking or sourcing current through a selected on of a plurality of devices under test (DUTs) on the semiconductor wafer, converting the current sourcing or sinking into a voltage, comparing the converted voltage against a linear voltage ramp, generating an output clock based on the comparison, and measuring a duty cycle of the output clock. In one embodiment, the duty cycle of the output clock is dependent on the current sinking or sourcing through the selected at least one of the plurality of DUTs on the wafer and electrical characteristics of material local to the specific area of the wafer where the selected one of the plurality of DUTs is located are determined based on the duty cycle of the output clock.