The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2025
Filed:
Aug. 16, 2023
Applicant:
Socionext Inc., Kanagawa, JP;
Inventor:
Hiroyuki Shimbo, Yokohama, JP;
Assignee:
SOCIONEXT INC., Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/00 (2025.01); H10D 62/10 (2025.01); H10D 84/85 (2025.01); H10D 84/90 (2025.01); H10D 89/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/907 (2025.01); H10D 62/10 (2025.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/912 (2025.01); H10D 84/961 (2025.01); H10D 84/964 (2025.01); H10D 84/966 (2025.01);
Abstract
Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. A standard cell having no logical function is disposed adjacent to a standard cell having a logical function. The standard cell includes nanowire FETs having nanowires and pads. The standard cell further includes dummy pads, which have no contribution to a logical function of a circuit.