The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Aug. 12, 2022
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yuta Nabuchi, Tokyo, JP;

Katsumi Eikyu, Tokyo, JP;

Atsushi Sakai, Tokyo, JP;

Akihiro Shimomura, Tokyo, JP;

Satoru Tokuda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H01L 21/265 (2006.01); H10D 30/01 (2025.01); H10D 30/66 (2025.01); H10D 62/17 (2025.01);
U.S. Cl.
CPC ...
H10D 62/111 (2025.01); H01L 21/26513 (2013.01); H10D 30/0297 (2025.01); H10D 30/668 (2025.01); H10D 62/393 (2025.01);
Abstract

A semiconductor device includes a cell region in which a plurality of unit cells are formed, and an outer peripheral region surrounding the cell region in plan view. Each of the plurality of unit cells includes a semiconductor substrate having a drift region, a body region, a source region, a pair of first column regions, and a gate electrode formed in a trench with a gate insulating film interposed therebetween. A well region is formed on a surface of the drift region in the outer peripheral region. A second column region is formed in the drift region below the well region and extends in Y and X directions so as to surround the cell region. The well region is connected to the body region, and the second column region is connected to the well region.


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