The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Dec. 16, 2022
Applicant:

Sumitomo Electric Industries, Ltd., Osaka, JP;

Inventor:

Yukihiro Tsuji, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); G03F 7/20 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H10D 30/47 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 30/015 (2025.01); G03F 7/201 (2013.01); G03F 7/203 (2013.01); H01L 21/0217 (2013.01); H01L 21/0271 (2013.01); H01L 21/0274 (2013.01); H01L 21/31144 (2013.01); H10D 30/061 (2025.01); H10D 30/4755 (2025.01); H10D 64/01 (2025.01); H10D 64/411 (2025.01);
Abstract

A method for manufacturing a semiconductor device, includes forming source and drain electrodes on a semiconductor layer provided above a substrate; forming a first insulating film covering a surface of the semiconductor layer, between the source and drain electrodes, forming a second insulating film on the first insulating film, forming a mask on the second insulating film, the mask having an opening between the source and drain electrodes in a plan view viewed in a direction perpendicular to a substrate surface, forming a first gate opening in the first insulating film and forming a second gate opening in the second insulating film, by etching the first and second insulating films through the opening, and forming a gate electrode on the first and second insulating films, the gate electrode making a Schottky contact with the semiconductor layer through the first and second gate openings.


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