The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Dec. 27, 2022
Applicant:

Hyundai Mobis Co., Ltd., Seoul, KR;

Inventors:

Min Gi Kang, Yongin-si, KR;

Hyuk Woo, Yongin-si, KR;

Tae Young Park, Yongin-si, KR;

Ju Hwan Lee, Yongin-si, KR;

Seon Hyeong Jo, Yongin-si, KR;

Seong Hwan Yun, Yongin-si, KR;

Tae Yang Kim, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 12/00 (2025.01); H10D 12/01 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/00 (2025.01);
U.S. Cl.
CPC ...
H10D 12/481 (2025.01); H10D 12/038 (2025.01); H10D 62/106 (2025.01); H10D 62/133 (2025.01); H10D 64/117 (2025.01);
Abstract

A power semiconductor device includes a plurality of gate electrodes configured to be recessed from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate, the second surface being opposite to the first surface, an emitter region configured to make contact with a trench and the first surface, being provided between respective ones of the plurality of gate electrodes, and including impurities of a first conductive type, a collector region configured to make contact with the second surface, and including second impurities of a second conductive type opposite to the first conductive type, a floating region extending toward the second surface in an extension direction of the trench while surrounding a bottom surface of the trench, and including the second impurities, and a trench emitter region interposed between the plurality of gate electrodes in the trench.


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