The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Sep. 28, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Daehwan Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02);
Abstract

A method of manufacturing a semiconductor device includes forming a stacked structure by stacking gate layers and interlayer insulating layers alternately on a substrate; and forming a channel structure passing through the stacked structure in a vertical direction, wherein the forming a channel structure includes forming an opening by etching the stacked structure; forming a gate insulating layer covering a side surface of the opening; forming a variable resistive material layer on the gate insulating layer; changing an oxygen vacancy concentration in a region of the variable resistive material layer by performing a plasma treatment process or an annealing process on the variable resistive material layer; forming a core insulating pattern covering the variable resistive material layer and filling at least a portion of the opening; and forming a pad pattern on the core insulating pattern.


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