The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Apr. 26, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jiwon Kim, Seoul, KR;

Jaeho Ahn, Seoul, KR;

Sungmin Hwang, Hwaseong-si, KR;

Joonsung Lim, Seongnam-si, KR;

Sukkang Sung, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/24 (2006.01); G11C 5/06 (2006.01); G11C 16/08 (2006.01); H01L 23/522 (2006.01); H01L 27/11539 (2017.01); H01L 27/11556 (2017.01); H01L 27/11573 (2017.01); H01L 27/11582 (2017.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); H10D 30/63 (2025.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); G11C 5/06 (2013.01); H01L 23/5226 (2013.01); H10B 43/27 (2023.02); H10D 30/63 (2025.01);
Abstract

A semiconductor device including a cell area including a first substrate, gate electrodes on the first substrate, a channel structure extending through the gate electrodes, cell contact plugs, a through contact plug, and first bonding pads, the first peripheral circuit area including second bonding pads on the first bonding pads; a second peripheral circuit area connected to the first peripheral circuit area; and a second substrate between the first peripheral circuit area and the second peripheral circuit area, the second substrate including a first surface in the first peripheral circuit area and a second surface in the second peripheral circuit area, wherein the second peripheral circuit area includes a device on the second surface, and a through electrode extending vertically through the second substrate and connected to the first peripheral circuit area.


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