Semiconductor element memory device

Abstract

A semiconductor element memory device is configured to perform a data hold operation of controlling voltages to be applied to a plate line, a word line, a source line, and a bit line to hold, in a semiconductor base, a positive hole group formed by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erase operation of controlling voltages to be applied to the plate line, the word line, the source line, and the bit line to discharge the positive hole group from the semiconductor base. The semiconductor element memory device includes a plurality of memory cells arranged in a matrix within a block, and constantly manages, using a controller circuit and a logical/physical conversion table, which physical block address of a dynamic flash memory corresponds to data stored in a logical block address.