The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2025
Filed:
Aug. 11, 2023
Applicant:
Apple Inc., Cupertino, CA (US);
Inventors:
Assignee:
Apple Inc., Cupertino, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); H01L 23/528 (2006.01); H10D 30/63 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
H10B 10/125 (2023.02); H01L 23/5286 (2013.01); H10B 10/18 (2023.02); H10D 30/63 (2025.01); H10D 64/252 (2025.01); H10D 64/518 (2025.01); H10D 84/85 (2025.01); H10D 84/856 (2025.01); H10D 89/10 (2025.01); H10B 10/12 (2023.02);
Abstract
A SRAM cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing along with stacked transistors to provide multiple transistors for implementation of inverters and pass gates in a memory cell. Various connection routes between components of the transistors (e.g., gates, sources, and drains) are made to allow cross-coupling between inverters in the memory cell.