Dynamic timing loop gain to compensate phase interpolation nonlinearities

Abstract

Integrated circuit transceivers having digital timing recovery loops with phase interpolation may incorporate dynamic loop gains to compensate for nonlinearities of the phase interpolation. An illustrative receiver circuit includes: a phase interpolator, a sampling element, a timing error estimator, and a feedback circuit. The phase interpolator provides a sampling signal by applying a phase shift to a clock signal in response to a phase control signal. The sampling element produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal. The timing error estimator produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal. The feedback circuit derives the phase control signal from the timing error signal using a scaling element configured to scale the estimated timing error by a scale factor that depends on the phase control signal.