The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Mar. 27, 2023
Applicant:

Lightmatter, Inc., Boston, MA (US);

Inventors:

Carlos Dorta-Quinones, Medford, MA (US);

Mykhailo Tymchenko, Melrose, MA (US);

Anthony Kopa, Somerville, MA (US);

Michael Gould, La Honda, CA (US);

Bradford Turcott, Georgetown, TX (US);

Robert Turner, Georgetown, TX (US);

Reza Baghdadi, Arlington, MA (US);

Shashank Gupta, Newton, MA (US);

Ajay Joshi, Lexington, MA (US);

Nicholas C. Harris, Boston, MA (US);

Darius Bunandar, Boston, MA (US);

Assignee:

Lightmatter, Inc., Boston, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/70 (2013.01); G02B 6/124 (2006.01); G02B 6/13 (2006.01); G02B 6/42 (2006.01); G02B 6/43 (2006.01); H04B 10/079 (2013.01); H04B 10/40 (2013.01); H04B 10/50 (2013.01); H04B 10/80 (2013.01); H04J 14/02 (2006.01);
U.S. Cl.
CPC ...
H04B 10/70 (2013.01); G02B 6/124 (2013.01); G02B 6/13 (2013.01); G02B 6/4215 (2013.01); G02B 6/4249 (2013.01); G02B 6/43 (2013.01); H04B 10/07953 (2013.01); H04B 10/40 (2013.01); H04B 10/50 (2013.01); H04B 10/803 (2013.01); H04B 10/808 (2013.01); H04J 14/0212 (2013.01);
Abstract

Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.


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